1. Field of the Invention
The present invention is directed toward the field of clock circuits, and more particularly to a programmable clock buffer circuit.
2. Art Background
Many clock distribution methods rely on the use of a zero delay buffer (ZDB) integrated circuit (IC). A typical application for such an IC is in a registered dual inline memory module (DIMM) 100, as shown in FIG. 1. The memory module input clock is fed to a phase-locked loop (PLL) based ZDB IC. The PLL-based IC 110 receives the input clock CKIN on a clock input 111. The PLL-based IC 110 outputs a plurality of intermediate clocks (CK1 to CKN) on a clock output 112. These signals are transmitted along an array of printed circuit hoard traces 102 to the DRAM ICs 120-1 to 120-N, and also to register ICs (not shown). Both the DRAM and register ICs are mounted on the memory module.
In addition, the clock feedback output 113 of the ZDB/PLL IC 110, CKfbo is routed on the module and fed back to the clock feedback input (CKfbi) on the feedback input 114 of the PLL-based IC 110. The PLL-based IC 110 ensures that the input and feedback clocks are aligned phase-wise. In addition, the length of the feedback wire is matched to those of the output clock wires to ensure a constant (small in typical applications) phase difference between the DRAM and register input clocks and the module input clock. This facilitates buffering with minimal delay, i.e. “zero delay” buffering, under ideal conditions.
Manufacturing variation in the printed circuit board (PCB), the DRAM, and the register ICs results in undesirable timing skews. Minimizing timing skew has typically required an arduous process that involves adjusting the capacitive load at the PLL feedback input. Typically this is done by adjusting the value of a discrete capacitor in order to equalize the skew between the DRAM input clocks and the memory module input clock. In addition, adjustment of the capacitive load at the register clock input must also be performed in order to eliminate skew between the clock at the register input and the clock input to the memory module.
The above methods increase manufacturing cost. Essentially the application specific delay must be hard-wired into the design of the printed circuit board or the IC itself. Thus, individual variations in the components used cannot be accounted for; instead the design-time skew minimization must be based on general statistics about the components that go into the application. This typically limits the application of these minimization techniques to a per-system or per-module basis, as a design change based on each lot of components would be too expensive.
What is needed is a method and/or device that permits minimization of timing skews in an economical fashion.
Further, what is needed is a method and/or device that, even when designed on a per-system or per-system basis, permits tuning at the per-lot level.